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Sr. Principle Analog/Mixed Signal Designer

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Location
San Jose, CA
Job Type
Direct Hire
Date
Jan 03, 2018
Job ID
2465787
The Principal/Sr.. Analog/Mixed-signal IC Design Engineer will be a key member in a small, dynamic IC Design team that develops high speed analog designs for optical communications products. He/she will architect, design, layout, measure and productize ultra-deep sub-micron based products. Essential Responsibilities:

Work with the mixed-signal team and system teams to specify the requirements
Responsible for analog circuit, layout design and testing of analog/mixed signal circuitry for high speed (>10GS/s) and high accuracy PLL/Fractional-N synthesizer designs
Required to lead a large block on a complex chip and mentor engineers.
Peer review of complex IC designs
Solid design methodology from conception to production
Work with packaging and hardware design team to ensure signal and power integrity specifications are met

Minimum Qualifications, Experience, Skills, Education and Certifications:
Principal/Sr. Analog/Mixed-Signal IC Design Engineer (PLL)
Typically requires a BSEE degree and 15 years of experience or an MS degree and 12 years of experience or a PhD and 10 years of experience.
Design, simulation and measurement of high speed ICs in the areas below: o
High Performance Phase Locked Loops  
Efficient clock Transmission/propagation  
PLL components (Reference clock circuits, phase-frequency detectors, charge pumps, VCO, modulus dividers).  
Voltage Regulators  
Clock Output Drivers 
Fractional-N Synthesizer for low jitter. 
Jitter attenuation techniques

Collaborative team player who can work independently.
Possessing a track record of innovation. Publications are a plus.

Highly Desired Skills:
Direct experience with electrical transceiver applications including backplane and cable communications.
Experience with FinFET technology or 40nm or below technology node
High-frequency layout experience a plus: a) Passive component design: inductors, transformers, transmission-lines, etc… b) Floorplanning (power/ground, digital/analog signal routing, etc…) c) Custom transistor layout.
Design for manufacturability: a) Characterization over PVT (Monte-Carlo analysis) b) Electromigration analysis (using Totem, or equivalent) c) Power and IR drop analysis
Laboratory Validation: a) Solid ESD laboratory practices and methodology b) Construction of test setup to test specific circuitry c) Experience in the use of high frequency test equipment (BERT, jitter analyzers, VNA, etc.)
Software Experience: a) Cadence (virtuoso) b) Spectre/APS c) Layout validation tools (Virtuoso or Calibre) d) Post-layout Extraction (Virtuoso or Calibre) e) EMX f) Mixed-signal simulations in AMS g) Matlab

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